Reliability Analysis of Buffer Stage in Mixed Signal Application

This paper discusses reliability analysis of a buffer circuit targeted for an analog to digital converter application. The circuit designed in a 32 nm high-κ metal gate CMOS technology was investigated by circuit simulation and sensitivity analysis. This analysis was conducted for realistic time varying (AC) stress. As aging effects, negative and positive bias temperature instability, conducting and non-conducting hot carrier injection are taken into consideration. The aging contributions of these effects on the different transistors in the buffer circuit and on different buffer performance figures are evaluated. Using these results, the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit is evaluated. The most severely affected performance due to aging is amplifier offset, which leads to time varying gain error in the ADC circuit.


Introduction
Non-constant field scaling in nanoscale CMOS technology has led to undesirable reliability issues due to effects such as Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Conducting and Non-Conducting Hot-Carrier Injection (HCI,NCHCI).Significant device level research is carried out on these effects (Grasser et al., 2007;Kaczer et al., 2009).However, since the superposition of these effects in a circuit is quite complex, the study of their impact on circuit level is still in a preliminary stage (Jha et al., 2005;Martin-Martinez et al., 2009;Chouard et al., 2010a).
This paper targets to investigate the impact of aging on a buffer stage designed for Analog to Digital Converter (ADC) application.The circuit was implemented and simulated us-Correspondence to: S.More (shailesh.more@tum.de)ing 32 nm high-κ metal gate regular V th nMOS and pMOS devices (Chen et al., 2008), so the effect of PBTI which appears due to high-κ is also present.The effects of buffer circuit degradation on ADC performance is demonstrated and the need for countermeasures is highlighted.The degradation effects are evaluated using a combination of sensitivity analysis and circuit simulation.This methodology as described in (More et al., 2010) was developed, as it needs considerably less computing effort than sole use of circuit simulation, and it provides more intuitive insight into the various degradation contributions.
Section 2 presents the models used for aging simulation.The investigated buffer circuit topology is shown in Sect.3. Section 4 discusses results of aging simulation of buffer circuits.The analytical evaluation of these degradation effects using sensitivity analysis, its comparison with simulation results and the observed impact on the circuit performance are presented in Sect. 5. Effects of buffer circuit aging on ADC performance and need of countermeasures are discussed in Sect.6.A conclusion is given in Sect.7.

Modeling of device degradation
Device degradation due to aging resulting from NBTI or PBTI mainly shifts the threshold voltage (V th ) of MOS transistors, whereas HCI and NCHCI reduce the transistor current (I d ) and also give a smaller contribution to the threshold voltage shift.This can be modeled by replacing the MOS-FET with an equivalent circuit shown in Fig. 1.The V th shifts are modeled by an equivalent voltage source vt shift in series to the gate terminal, the hot carrier effects by a current controlled current source (CCCS) I d shift between the drain and source terminal.The threshold voltage shift by each of the BTI effects can be modeled by ( V th ) BTI as in Eq. ( 1 Device degradation due to aging resulting from NBTI or PBTI mainly shifts the threshold voltage (V th ) of MOS transistors, whereas HCI and NCHCI reduce the transistor current (I d ) and also give a smaller contribution to the threshold voltage shift.This can be modeled by replacing the MOS-  FET with an equivalent circuit shown in Figure 1.The V th shifts are modeled by an equivalent voltage source vt shif t in series to the gate terminal, the hot carrier effects by a current controlled current source (CCCS) Id shif t between the drain and source terminal.The threshold voltage shift by each of the BTI effects can be modeled by (∆V th ) BT I as in equation (1).BTI stands for NBTI in pMOS transistors and for PBTI in nMOS transistors.The current degradation is modeled by equation (2), separately for HCI and NCHCI.The values of the equivalent sources are determined using (1)-( 2), which describe the relation of different contributing factors to the overall degradation, similar to (Martin-Martinez et al., 2009;Huard et al., 2009).The total vt shif t is the sum of two contributions, see equation (3).The total current degradation is modeled by equation ( 4).The model parameters were fitted to single device stress measurements.
For the evaluations based on circuit simulation and to account for time varying (AC) stress, the aging simulation tool RelXpert T M (RelXpert, 2010) was used, which employs the above discussed models.

Buffer Circuit for ADC Application
The schematic for the fully differential buffer circuit is illustrated in Fig. 2a.It basically consists of an Operational Transconductance Amplifier (OTA), resistors and switches.Capacitors of 2pF are used to emulate the load of a Digital to Analog Converter (DAC) connected at the output of the buffer circuit.The primary function of this buffer circuit in the charge distribution based successive approxima- The used OTA is illustrated in Fig. 4. It is a two stage folded cascode amplifier with Miller compensation.Implementing this circuit using regular V th pMOS and nMOS transistors with V th ≈0.45V and supply V DD =1V leads to significant challenges in using the common mode voltage V cm =0.5V at the gate of input differential pair (N 0 and N 1 ) and maintaining the tail transistor (N 3 ) in saturation.To overcome this problem a simple level shifting circuit as depicted in Fig. 2b was used at the input of the OTA.This circuit shifts each input signal (V in ) of the OTA with V cm =0.5V to a new shifted signal (S vin ) depending on the difference between the common mode and the shift voltage (V shif t ).

Aging Simulation results
OTA performances at nominal condition (before stress, Temp=25 • C and V DD =1V) are listed below.Here V of f set refers to output referred offset.Eq. ( 2), separately for HCI and NCHCI.The values of the equivalent sources are determined using Eqs.( 1)-( 2), which describe the relation of different contributing factors to the overall degradation, similar to (Martin-Martinez et al., 2009;Huard et al., 2009).The total vt shift is the sum of two contributions, see Eq. ( 3).The total current degradation is modeled by Eq. ( 4).The model parameters were fitted to single device stress measurements. (2) For the evaluations based on circuit simulation and to account for time varying (AC) stress, the aging simulation tool RelXpert TM (RelXpert, 2010) was used, which employs the above discussed models.

Buffer circuit for ADC application
The schematic for the fully differential buffer circuit is illustrated in Fig. 2a.-Martinez et al., 2009;Huard et al., 2009).The total vt shif t is the sum of two contributions, see equation (3).The total current degradation is modeled by equation ( 4).The model parameters were fitted to single device stress measurements.
For the evaluations based on circuit simulation and to account for time varying (AC) stress, the aging simulation tool RelXpert T M (RelXpert, 2010) was used, which employs the above discussed models.

Buffer Circuit for ADC Application
The schematic for the fully differential buffer circuit is illustrated in Fig. 2a.It basically consists of an Operational Transconductance Amplifier (OTA), resistors and switches.Capacitors of 2pF are used to emulate the load of a Digital to Analog Converter (DAC) connected at the output of the buffer circuit.The primary function of this buffer circuit in the charge distribution based successive approximation (SAR) ADC as depicted in Fig. 3 (Fulde et al., 2009), is to drive the DAC implemented using capacitors, within a short settling time (≈4ns) with reference voltage (V ref ±) The used OTA is illustrated in Fig. 4. It is a two stage folded cascode amplifier with Miller compensation.Implementing this circuit using regular V th pMOS and nMOS transistors with V th ≈0.45V and supply V DD =1V leads to significant challenges in using the common mode voltage V cm =0.5V at the gate of input differential pair (N 0 and N 1 ) and maintaining the tail transistor (N 3 ) in saturation.To overcome this problem a simple level shifting circuit as depicted in Fig. 2b was used at the input of the OTA.This circuit shifts each input signal (V in ) of the OTA with V cm =0.5V to a new shifted signal (S vin ) depending on the difference between the common mode and the shift voltage (V shif t ).

Aging Simulation results
OTA performances at nominal condition (before stress, Temp=25 • C and V DD =1V) are listed below.Here V of f set refers to output referred offset.2009; Huard et al., 2009).The total vt shif t is the sum of two contributions, see equation (3).The total current degradation is modeled by equation ( 4).The model parameters were fitted to single device stress measurements. (3) For the evaluations based on circuit simulation and to account for time varying (AC) stress, the aging simulation tool RelXpert T M (RelXpert, 2010) was used, which employs the above discussed models.

Buffer Circuit for ADC Application
The schematic for the fully differential buffer circuit is illustrated in Fig. 2a.It basically consists of an Operational Transconductance Amplifier (OTA), resistors and switches.Capacitors of 2pF are used to emulate the load of a Digital to Analog Converter (DAC) connected at the output of the buffer circuit.The primary function of this buffer circuit in the charge distribution based successive approximation (SAR) ADC as depicted in Fig. 3 (Fulde et al., 2009), is to drive the DAC implemented using capacitors, within a short settling time (≈4ns) with reference voltage (V ref ±) V cm =0.5V at the gate of input differential pair (N 0 and N 1 ) and maintaining the tail transistor (N 3 ) in saturation.To overcome this problem a simple level shifting circuit as depicted in Fig. 2b was used at the input of the OTA.This circuit shifts each input signal (V in ) of the OTA with V cm =0.5V to a new shifted signal (S vin ) depending on the difference between the common mode and the shift voltage (V shif t ).

Aging Simulation results
OTA performances at nominal condition (before stress, Temp=25 • C and V DD =1V) are listed below.Here V of f set refers to output referred offset.the buffer circuit.The primary function of this buffer circuit in the charge distribution based successive approximation (SAR) ADC as depicted in Fig.
3 (Fulde et al., 2009), is to drive the DAC implemented using capacitors, within a short settling time (≈4 ns) with reference voltage (V ref ±) and analog input (a in ±) during different phases of the clock signals that control the switches.The clock signals are shown only schematically, not displaying the more complex clocking during the ADC operation.The used OTA is illustrated in Fig. 4. It is a two stage folded cascode amplifier with Miller compensation.Implementing this circuit using regular V th pMOS and nMOS transistors with V th ≈ 0.45 V and supply V DD = 1 V leads to significant challenges in using the common mode voltage V cm = 0.5 V at the gate of input differential pair (N 0 and N 1 ) and maintaining the tail transistor (N 3 ) in saturation.To overcome this problem a simple level shifting circuit as depicted in Fig. 2b was used at the input of the OTA.This circuit shifts each input signal (V in ) of the OTA with V cm = 0.5 V to a new shifted signal (S vin ) depending on the difference between the common mode and the shift voltage (V shift ).
Adv. Radio Sci., 9, 225-230, 2011 www.adv-radio-sci.net/9/225/2011/The aging simulations were performed using AC input signals of a inp =0.6V p−p , 1.1MHz sine wave, and a inn =0.6V p−p , 1.1MHz, 180 • phase shifted sine wave.The bias voltages are ). Fig. 5 illustrates the gain Bode plot for the OTA at different V DD and T emp stress conditions, simulated for stress time (Age) of 10 years.In the OTA circuit, mainly the bias current through transistors N 3 and N 10 decides the gain, phase margin and bandwidth.These transistors see only limited gate and drain voltages, so no remarkable degradation occurs.Consequently, it can be observed from Fig. 5 and the results given in Table .1 that no significant performance degradation of these parameters (less than 1%) was observed after aging since this bias current is not affected.This shows that the current mirror structures are robust towards aging effects.
The spectral behavior of the buffer circuit was studied to see if any significant non-linearity is introduced due to circuit aging.The simulation results are depicted in Fig. 6 and Fig. 7.There is no significant difference in the spectral performances before and after aging.
However in closed loop configuration aging degradation leads to considerable V of f set in the differential output pair due to the asymmetry of the stress conditions on these two transistors: P5 is connected to V out + and sees high positive voltages, whereas P4 sees much lower voltages at V out −. Table 2 summarizes the degradation-induced output referred V of f set simulated at different V DD and T emp stress condi- tions for an age of 10 years.The corresponding input referred offset is obtained by dividing these values with the gain of the OTA, and it is found to be quite small due to a large gain.

Impact of Aging on circuit performance
To study more closely the particular contribution of each transistor in the buffer circuit to V of f set , we evaluate its sensitivity towards V th and I d shift resulting from circuit aging.V of f set is calculated in this sensitivity analysis based analytical evaluation (More et al., 2010) using equation ( 5).
For each transistor (T n ), the sensitivity (S VT n ) of V of f set towards V th shift as well the sensitivity (S IT n ) towards I d shift is determined by circuit simulation and is then multi-

Aging simulation results
OTA performances at nominal condition (before stress, Temp = 25 • C and V DD = 1 V) are listed below.Here V offset refers to output referred offset.
DC Gain = 59.71 dB Gain Bandwidth = 736.8MHz Phase Margin = 89 The aging simulations were performed using AC input signals of a inp = 0.6V p−p , 1.1MHz sine wave, and a inn = 0.6V p−p , 1.1 MHz, 180 • phase shifted sine wave.The bias voltages are V refp = 0.8 V, V refn = 0.2 V, V cm = 0.5 V, V shift = 0.8 V, Clk = 20 MHz). Figure 5 illustrates the gain Bode plot for the OTA at different V DD and Temp stress conditions, simulated for stress time (Age) of 10 years.In the OTA circuit, mainly the bias current through transistors N 3 and N 10 decides the gain, phase margin and bandwidth.These transistors see only limited gate and drain voltages, so no remarkable degradation occurs.Consequently, it can be observed from Fig. 5 and the results given in Table 1 that no significant performance degradation of these parameters (less than 1%) was observed after aging since this bias current is not affected.This shows that the current mirror structures are robust towards aging effects.
The spectral behavior of the buffer circuit was studied to see if any significant non-linearity is introduced due to circuit aging.The simulation results are depicted in Figs. 6 and  7.There is no significant difference in the spectral performances before and after aging.The aging simulations were performed using AC input signals of a inp =0.6V p−p , 1.1MHz sine wave, and a inn =0.6V p−p , 1.1MHz, 180 • phase shifted sine wave.The bias voltages are ). Fig. 5 illustrates the gain Bode plot for the OTA at different V DD and T emp stress conditions, simulated for stress time (Age) of 10 years.In the OTA circuit, mainly the bias current through transistors N 3 and N 10 decides the gain, phase margin and bandwidth.These transistors see only limited gate and drain voltages, so no remarkable degradation occurs.Consequently, it can be observed from Fig. 5 and the results given in Table .1 that no significant performance degradation of these parameters (less than 1%) was observed after aging since this bias current is not affected.This shows that the current mirror structures are robust towards aging effects.
The spectral behavior of the buffer circuit was studied to see if any significant non-linearity is introduced due to circuit aging.The simulation results are depicted in Fig. 6 and Fig. 7.There is no significant difference in the spectral performances before and after aging.
However in closed loop configuration aging degradation leads to considerable V of f set in the differential output pair due to the asymmetry of the stress conditions on these two transistors: P5 is connected to V out + and sees high positive voltages, whereas P4 sees much lower voltages at V out −. Table 2 summarizes the degradation-induced output referred V of f set simulated at different V DD and T emp stress condi- tions for an age of 10 years.The corresponding input referred offset is obtained by dividing these values with the gain of the OTA, and it is found to be quite small due to a large gain.

Impact of Aging on circuit performance
To study more closely the particular contribution of each transistor in the buffer circuit to V of f set , we evaluate its sensitivity towards V th and I d shift resulting from circuit aging.V of f set is calculated in this sensitivity analysis based analytical evaluation (More et al., 2010) using equation ( 5).
For each transistor (T n ), the sensitivity (S VT n ) of V of f set towards V th shift as well the sensitivity (S IT n ) towards I d shift is determined by circuit simulation and is then multi-  The aging simulations were performed using AC input signals of a inp =0.6V p−p , 1.1MHz sine wave, and a inn =0.6V p−p , 1.1MHz, 180 • phase shifted sine wave.The bias voltages are ). Fig. 5 illustrates the gain Bode plot for the OTA at different V DD and T emp stress conditions, simulated for stress time (Age) of 10 years.In the OTA circuit, mainly the bias current through transistors N 3 and N 10 decides the gain, phase margin and bandwidth.These transistors see only limited gate and drain voltages, so no remarkable degradation occurs.Consequently, it can be observed from Fig. 5 and the results given in Table .1 that no significant performance degradation of these parameters (less than 1%) was observed after aging since this bias current is not affected.This shows that the current mirror structures are robust towards aging effects.
The spectral behavior of the buffer circuit was studied to see if any significant non-linearity is introduced due to circuit aging.The simulation results are depicted in Fig. 6 and Fig. 7.There is no significant difference in the spectral performances before and after aging.
However in closed loop configuration aging degradation leads to considerable V of f set in the differential output pair due to the asymmetry of the stress conditions on these two transistors: P5 is connected to V out + and sees high positive voltages, whereas P4 sees much lower voltages at V out −. Table 2 summarizes the degradation-induced output referred V of f set simulated at different V DD and T emp stress condi- tions for an age of 10 years.The corresponding input referred offset is obtained by dividing these values with the gain of the OTA, and it is found to be quite small due to a large gain.

Impact of Aging on circuit performance
To study more closely the particular contribution of each transistor in the buffer circuit to V of f set , we evaluate its sensitivity towards V th and I d shift resulting from circuit aging.V of f set is calculated in this sensitivity analysis based analytical evaluation (More et al., 2010) using equation ( 5).
For each transistor (T n ), the sensitivity (S VT n ) of V of f set towards V th shift as well the sensitivity (S IT n ) towards I d shift is determined by circuit simulation and is then multi- However in closed loop configuration aging degradation leads to considerable V offset in the differential output pair due to the asymmetry of the stress conditions on these two transistors: P5 is connected to V out + and sees high positive voltages, whereas P4 sees much lower voltages at V out −. Table 2 summarizes the degradation-induced output referred V offset simulated at different V DD and Temp stress conditions for an age of 10 years.The corresponding input referred offset is obtained by dividing these values with the gain of the OTA, and it is found to be quite small due to a large gain.

Impact of aging on circuit performance
To study more closely the particular contribution of each transistor in the buffer circuit to V offset , we evaluate its sensitivity towards V th and I d shift resulting from circuit aging.V offset is calculated in this sensitivity analysis based analytical evaluation (More et al., 2010) using Eq. ( 5).For each transistor (T n ), the sensitivity (S V T n ) of V offset towards V th shift as well the sensitivity (S I T n ) towards I d shift is determined by circuit simulation and is then multiplied with the respective V th and I d shifts.Finally, the total offset voltage shift is summed up.The results of this analysis are matching closely with results obtained by circuit simulation using RelXpert, as illustrated in Table .2.   plied with the respective V th and I d shifts.Finally, the total offset voltage shift is summed up.The results of this analysis are matching closely with results obtained by circuit simulation using RelXpert, as illustrated in Table .2.
The sensitivity of V of f set towards V th and I d shift of all transistors in the buffer circuit is illustrated in Fig. 8 and Fig. 9.
The data in Fig. 10  of V of f set .The NBTI degradations of the pMOS transistors P 0 and P 1 in Fig. 12 are of equal magnitude and compensate each other in their effect on the offset, since they see the same gate to source voltage coming from the common mode (cm) feedback circuit.Thus their NBTI degradation causes negligible V of f set change.The same holds true for transistors P 2 and P 3 .As mentioned before, the dominant contribution to V of f set due to V th shift comes from the pMOS transistors of the output stage, P 4 resulting from HCI (50.56%) and NBTI (49.44%) followed by P 5 resulting from HCI (38.87%) and NBTI (61.13%).Although the sensitivity of V of f set towards V th shift of transistors P 4 and P 5 is low (±12.67) the differ- The sensitivity of V offset towards V th and I d shift of all transistors in the buffer circuit is illustrated in Figs. 8 and 9.
The data in Figs. 10 and 11 represents V th and I d shift respectively, in different transistors of the OTA circuit resulting due to aging.The V th shift is a combined effect of BTI and HCI and I d shift is a combined effect of HCI and NCHCI degradation.
In Figs. 12 and 13 the contributions to V offset due to aging of the individual transistors are given.These are the theoretical intermediate results obtained by multiplying the V th and I d shift for each transistor with respective sensitivity of V offset .The NBTI degradations of the pMOS transistors P 0 and P 1 in Fig. 12 are of equal magnitude and compensate each other in their effect on the offset, since they see the same gate to source voltage coming from the common mode (cm) feedback circuit.Thus their NBTI degradation causes negligible V offset change.The same holds true for transistors P 2 and P 3 .As mentioned before, the dominant contribution to V offset due to V th shift comes from the pMOS transistors of the output stage, P 4 resulting from HCI (50.56%) and NBTI (49.44%) followed by P 5 resulting from HCI (38.87%) and NBTI (61.13%).Although the sensitivity of V offset towards V th shift of transistors P 4 and P 5 is low (±12.67) the difference between their V th shifts leads to a significant impact on V offset .
Figure 13 shows that the dominant contribution to V offset due to I d shift comes from pMOS transistors P 4 and P 5 re- plied with the respective V th and I d shifts.Finally, the total offset voltage shift is summed up.The results of this analysis are matching closely with results obtained by circuit simulation using RelXpert, as illustrated in Table .2.
The sensitivity of V of f set towards V th and I d shift of all transistors in the buffer circuit is illustrated in Fig. 8 and Fig. 9.The data in Fig. 10 and Fig. 11 represents V th and I d shift respectively, in different transistors of the OTA circuit resulting due to aging.The V th shift is a combined effect of BTI and HCI and I d shift is a combined effect of HCI and NCHCI degradation.
In Fig. 12 and Fig. 13 the contributions to V of f set due to aging of the individual transistors are given.These are the theoretical intermediate results obtained by multiplying the V th and I d shift for each transistor with respective sensitivity  plied with the respective V th and I d shifts.Finally, the total offset voltage shift is summed up.The results of this analysis are matching closely with results obtained by circuit simulation using RelXpert, as illustrated in Table .2.  sulting from HCI degradation.Although the sensitivity of V offset towards I d shift of transistors P 4 and P 5 is low (±1.09) the difference between their I d shift leads to a significant impact on V offset .The effects of transistors P 2 and P 3 again cancel each other.Comparison of Figs. 12 and 13 shows that V th shift is the dominant contribution (85.9%) to V offset compared to I d shift (14.1%).
In summary, the degradation due to circuit aging affects almost all transistors in the buffer circuit.The most degraded circuit performance is V offset .Since the OTA in the buffer circuit always operates in closed loop configuration, its input transistors see smaller stress compared to the output stage transistors.Simulation results show that these output transistors are the main contributors to V offset .The results presented here are in-line with experimental findings from (Chouard et al., 2010b  of V of f set .The NBTI degradations of the pMOS transistors P 0 and P 1 in Fig. 12 are of equal magnitude and compensate each other in their effect on the offset, since they see the same gate to source voltage coming from the common mode (cm) feedback circuit.Thus their NBTI degradation causes negligible V of f set change.The same holds true for transistors P 2 and P 3 .As mentioned before, the dominant contribution to V of f set due to V th shift comes from the pMOS transistors of the output stage, P 4 resulting from HCI (50.56%) and NBTI (49.44%) by P 5 resulting from HCI (38.87%) and NBTI (61.13%).Although the sensitivity of V of f set towards V th shift of transistors P 4 and P 5 is low (±12.67) the difference between their V th shifts leads to a significant impact on V of f set .
Fig. 13 shows that the dominant contribution to V of f set due to I d shift comes from pMOS transistors P 4 and P 5 resulting from HCI degradation.Although the sensitivity of V of f set towards I d shift of transistors P 4 and P 5 is low

Impact on ADC Performance
To study the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit, a 12bit SAR ADC with charge redistribution as illustrated in Fig. 3 was modeled.All the circuit blocks were modeled as ideal elements using Verilog-A to reduce the complexity and the simulation time.A stress induced input referred offset as high as 5mV has been reported for an OTA circuit operated in closed loop configuration (Chouard et al., 2010b).So an input referred offset of 10mV was assumed as worst case condition for the simulations.The converter was simulated with a clock frequency of 33.33MHz, and a conversion rate of 1.19MS/s was used with V ref p =0.8V, V ref n =0.2V and V DD =1V.
The simulated differential non-linearity (DNL) and integral non-linearity (INL) are shown in Fig. 14.The resultant ENOB is 11.98 bits, which shows that the linearity of this SAR ADC is not affected by the aged buffer circuit.It was confirmed by simulations that also the spectral characteristics of the ADC were not affected.However, the transfer characteristics depicted in Fig. 15 shows that a gain error arises

Impact on ADC performance
To study the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit, a 12 bit SAR ADC with charge redistribution as illustrated in Fig. 3 was modeled.All the circuit blocks were modeled as ideal elements using Verilog-A to reduce the complexity and the simulation time.A stress induced input referred offset as high as 5mV has been reported for an OTA circuit operated in closed loop configuration (Chouard et al., 2010b).So an input referred offset of 10 mV was assumed as worst case condition for the simulations.The converter was simulated with a clock frequency of 33.33 MHz, and a conversion rate of 1.19 MS/s was used with V refp = 0.8 V, V refn = 0.2 V and V DD = 1 V.
The simulated differential non-linearity (DNL) and integral non-linearity (INL) are shown in Fig. 14.The resultant (±1.09) the difference between their I d shift leads to a significant impact on V of f set .The effects of transistors P 2 and P 3 again cancel each other.Comparison of Figs. 12 and 13 shows that V th shift is the dominant contribution (85.9%) to V of f set compared to I d shift (14.1%).
In summary, the degradation due to circuit aging affects almost all transistors in the buffer circuit.The most degraded circuit performance is V of f set .Since the OTA in the buffer circuit always operates in closed loop configuration, its input transistors see smaller stress compared to the output stage transistors.Simulation results show that these output transistors are the main contributors to V of f set .The results presented here are in-line with experimental findings from (Chouard et al., 2010b).

Impact on ADC Performance
To study the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit, a 12bit SAR ADC with charge redistribution as illustrated in Fig. 3 was modeled.All the circuit blocks were modeled as ideal elements using Verilog-A to reduce the complexity and the simulation time.A stress induced input referred offset as high as 5mV has been reported for an OTA circuit operated in closed loop configuration (Chouard et al., 2010b).So an input referred offset of 10mV was assumed as worst case condition for the simulations.The converter was simulated with a clock frequency of 33.33MHz, and a conversion rate of 1.19MS/s was used with V ref p =0.8V, V ref n =0.2V and V DD =1V.
The simulated differential non-linearity (DNL) and integral non-linearity (INL) are shown in Fig. 14.The resultant ENOB is 11.98 bits, which shows that the linearity of this SAR ADC is not affected by the aged buffer circuit.It was confirmed by simulations that also the spectral characteristics of the ADC were not affected.However, the transfer characteristics depicted in Fig. 15 shows that a gain error arises ENOB is 11.98 bits, which shows that the linearity of this SAR ADC is not affected by the aged buffer circuit.It was confirmed by simulations that also the spectral characteristics of the ADC were not affected.However, the transfer characteristics depicted in Fig. 15 shows that a gain error arises in the converter.All SAR ADC's having resolution (1 LSB) value smaller than the worst case input referred offset will be affected by aging degradation in this manner, with magnitude depending on the offset.There are proven methods to correct a gain error.But it is important to note that this error will vary over time.Hence special countermeasures need to be implemented to guarantee a stable and correct circuit function for the whole lifetime of the circuit.with device aging.It was found that the most severely affected performance due to aging is amplifier offset, which leads to time varying gain error in an ADC circuit.Comparing Bode plots and spectal characteristics of the buffer circuit before and after aging, it could be observed that the amplifier gain, bandwidth, phase margin and spectral performance are not degraded due to aging.In a successive approximation ADC, the main effect due to aging is a time varying gain error.This leads to the conclusion that there is a need to implement special countermeasures in ADCs which correct for time varying errors resulting from stress induced degradation.

Conclusions
In this paper a buffer circuit designed in a 32 nm high-k, metal gate technology was analyzed by simulation for reliability with device aging.It was found that the most severely affected performance due to aging is amplifier offset, which leads to time varying gain error in an ADC circuit.Comparing Bode plots and spectal characteristics of the buffer circuit before and after aging, it could be observed that the amplifier gain, bandwidth, phase margin and spectral performance are not degraded due to aging.In a successive approximation ADC, the main effect due to aging is a time varying gain error.This leads to the conclusion that there is a need to implement special countermeasures in ADCs which correct for time varying errors resulting from stress induced degradation.

Fig. 2 .
Fig. 2. Schematic of buffer and DC level shifting circuit

Fig. 2 .
Fig. 2. Schematic of buffer and DC level shifting circuit.

Fig. 5 .
Fig. 5. Simulated Gain (dB) resulting in the buffer circuit for a stress time of 10 Yrs

Fig. 5 .
Fig. 5. Simulated Gain (dB) resulting in the buffer circuit for a stress time of 10 Yrs

Fig. 5 .
Fig. 5. Simulated Gain (dB) resulting in the buffer circuit for a stress time of 10 Yrs

Fig. 8 .Fig. 9 .
Fig. 8. Sensitivity of V of f set towards V th shift of different transistors in the OTA circuit

Fig. 8 .
Fig. 8. Sensitivity of V offset towards V th shift of different transistors in the OTA circuit.

TransistorsFig. 8 .Fig. 9 .
Fig. 8. Sensitivity of V of f set towards V th shift of different transistors in the OTA circuit

Fig. 8 .Fig. 9 .
Fig. 8. Sensitivity of V of f set towards V th shift of different transistors in the OTA circuit

Fig. 10 .
Fig. 10.NBTI, PBTI and HCI degradation component in V th shift simulated for stress time of 10Yrs at V DD = 1 V and Temp = 85 • C.

Fig. 11 .P1
Fig. 11.HCI and NCHCI degradation component in I d shift simulated for stress time of 1 Yrs at V DD = 1 V and Temp = 85 • C. S.More et al.: Reliability Analysis of Buffer Stage 5

Fig. 12 .Fig. 13 .Fig. 14 .
Fig. 12. Contribution to V of f set due to V th shift resulting from NBTI, PBTI and HCI degradation, simulated for stress time of 10Yrs at V DD =1V and Temp=85 • C

Fig. 12 .
Fig. 12. Contribution to V offset due to V th shift resulting from NBTI, PBTI and HCI degradation, simulated for stress time of 10 Yrs at V DD = 1 V and Temp = 85 • C.

Fig. 12 .Fig. 13 .
Fig. 12. Contribution to V of f set due to V th shift resulting from NBTI, PBTI and HCI degradation, simulated for stress time of 10Yrs at V DD =1V and Temp=85 • C

Fig. 14 .
Fig. 14.Simulated DNL and INL of ADC with 10mV input referred offset in the buffer circuit.

Fig. 15 .
Fig. 15.Simulated input vs. output characteristics of ADC with (10mV) and without input referred offset in the buffer circuit

Fig. 15 .
Fig. 15.Simulated input vs. output characteristics of ADC with (10 mV) and without input referred offset in the buffer circuit.
S.More et al.:Reliability Analysis of Buffer Stage 3

Table 2 .
referred V of f set in (mV) resulting in the buffer circuit for a stress time of 10 Yrs

Table 1 .
S.More et al.:Reliability Analysis of Buffer Stage 3 Simulated Gain(dB)/ Phase margin( • )/ Gain Bandwidth(MHz) resulting for a stress time of 10 Yrs

Table 2 .
referred Voffset in (mV) resulting in the buffer circuit for a stress time of 10 Yrs

Table 2 .
referred Voffset in (mV) resulting in the buffer circuit for a stress time of 10 Yrs Fig. 7. FFT Spectrum results from degraded netlist.

Table 2 .
Output referred V offset in (mV) resulting in the buffer circuit for a stress time of 10 Yrs. ).