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Advances in Radio Science An open-access journal of the U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V.
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Volume 8
Adv. Radio Sci., 8, 295–305, 2010
https://doi.org/10.5194/ars-8-295-2010
© Author(s) 2010. This work is distributed under
the Creative Commons Attribution 3.0 License.
Adv. Radio Sci., 8, 295–305, 2010
https://doi.org/10.5194/ars-8-295-2010
© Author(s) 2010. This work is distributed under
the Creative Commons Attribution 3.0 License.

  22 Dec 2010

22 Dec 2010

Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

T. Jungeblut1, C. Puttmann1, R. Dreesen2, M. Porrmann1, M. Thies2, U. Rückert3, and U. Kastens2 T. Jungeblut et al.
  • 1University of Paderborn, System and Circuit Technology, Germany
  • 2University of Paderborn, Department of Computer Science, Germany
  • 3Bielefeld University, Cognitive Interaction Technology, Germany

Abstract. The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions.

Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

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