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Advances in Radio Science An open-access journal of the U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V.
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Volume 5
Adv. Radio Sci., 5, 285-290, 2007
https://doi.org/10.5194/ars-5-285-2007
© Author(s) 2007. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.
Adv. Radio Sci., 5, 285-290, 2007
https://doi.org/10.5194/ars-5-285-2007
© Author(s) 2007. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

  13 Jun 2007

13 Jun 2007

Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects

M. Fulde1, J. P. Engelstädter2,3, G. Knoblinger2, and D. Schmitt-Landsiedel1 M. Fulde et al.
  • 1Institute of Technical Electronics, Technical University Munich, Germany
  • 2Infineon Technologies AG, Villach, Austria
  • 3Department of Electrical Engineering, RWTH Aachen University, Aachen, Germany

Abstract. Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub-45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (gm/gDS) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies. To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks.

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