2.1 High throughput turbo-decoder hardware architectures

State-of-the-art Turbo-Code decoder hardware architectures can be classified based on their approach on how to parallelize the inherrently serial max-Log-Map algorithm:

Parallel Map. (PMAP) – decoders use spacial parallelism by splitting the code block trellis into sub-trellises (or sub-blocks) that are decoded on p parallel sub-decoder cores (see Fig. 2a) and parallel windowed processing of forward and backward recursions within the cores. Implementations which use the PMAP architecture are reported, for example by Belfanti et al. (2013), Sun and Cavallaro (2010), Ilnseher et al. (2012) and Shrestha and Paily (2014).

Fully Pipelined Map. (FPMAP) – decoders implement a fully parallel processing of both component codes Li et al. (2016b), Li et al. (2016a) (see Fig. 2b). The recently published architecture promises very high throughput and can be seen as an extreme case of the PMAP architecture where each sub-trellis essentially consists of one step of the original trellis.

Pipelined Map. (XMAP) – decoders, as reported by Ilnseher et al. (2010) or Wang et al. (2014), unroll and pipeline the recursions, a functional parallelization. Each clock cycle, one continuous sub-trellis (window) is fed into the “X”-shaped pipeline structure (see Fig. 2c) which gives the decoder its name.

Figure 2Decoding of a code word of size K on a: (a) PMAP decoder with p sub-decoder cores, (b) FPMAP decoder, (c) XMAP decoder with p pipeline stages; $\mathrm{\Pi }/{\mathrm{\Pi }}^{-\mathrm{1}}$: Interleaver/Deinterleaver.

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Spliting up the code block trellis into sub-blocks or windows, however, weakens the protection of the bits at the sub-block/window borders, because state metric information is lost. Since the FPMAP architecture leads to sub-trellises consisting of only one step, this effect is more pronounced for the FPMAP and is the reason why it needs more iterations than the other decoder types, even at rate 1∕3. For the other decoder types, the state metrics at the sub-block borders can to be estimated.

Figure 3Cross-layer Optimization.

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The estimation for the state metrics at the sub-block borders can be taken from a warm-up recursion phase (acquisition – ACQ) or from the state metric calculations of the previous iteration (Next Iteration Initialization – NII) as proposed by Dielissen and Huiskens (2000). For very small windows and/or high code rates, a combination of ACQ and NII can be used to mitigate very long acquisition lengths (see Roth et al., 2014). Note, that state-of-the-art Turbo-Code decoders expect their input depunctured to rate 1∕3 and thus do not take into account the puncturing pattern that is used to adapt the rate.

For small code block sizes K and large degrees of parallelism p, the sub-block sizes $S=K/p$ become very small. Thus, the achievable level of parallelism for a desired Quality of Service (QoS) is limited, especially for high code rates. Therefore, in state-of-the-art PMAP decoders, smaller code words are only decoded on a fraction of the available sub-decoder cores and the smallest code block sizes (i.e. $\mathrm{40}\le K\le \mathrm{248}$) are decoded only using a single sub-decoder core while the others remain idle.

2.2 LTE-A turbo coding for DL-SCH

The LTE standard organizes the data to be transmitted over the Downlink Shared Channel (DL-SCH) in each transmission time interval (TTI) in transport blocks (TB) which have sizes ranging from 16 to 97 896 bit (see Third Generation Partnership Project, 2016). The DL-SCH channel coding scheme is depicted in Fig. 1b. The uncoded transport block is first attached with a 24 bit CRC for the hybrid automatic repeat request (HARQ) protocol. Then, the transport block is divided into smaller code blocks if its size (with attached CRC) is larger than 6144 bit. This process is called code block segmentation. After segmentation, the code blocks contain a maximum of 6120 bits and are each attached with another 24 bit CRC (the code block CRC) before being encoded with a rate 1∕3 Turbo-Code. The code block segmentation step is followed by a circular buffer rate matching to adapt the code rate by puncturing or repetition. Last step is the code block concatenation.

3.1 Iteration balancing

With a CRC based iteration control, the decoding process is terminated early, as soon as the CRC on the decoded code word evaluates to zero. Otherwise, the decoding is continued until a maximum number of half-iterations ($n_{\mathrm{HI}}^{\max }$) is reached. This is depicted in Fig. 4b, whereas Fig. 4a illustrates the case without early stopping.

For iteration balancing, the CRC based iteration control, which is used to terminate the decoding process early in the event of successful decoding, is extended to account for the TB structure on system level. Iteration balancing makes use of the fact, that most code blocks are decoded in less than $n_{\mathrm{HI}}^{\max }$ half-iterations and that large code block buffers are available in the rate matching unit for the incremental redundancy of the HARQ (see Weithoffer and Wehn, 2017a). Instead of stopping the decoder after $n_{\mathrm{HI}}^{\max }$ half-iterations and signaling a failed decoding if the CRC does not evaluate to zero, with iteration balancing a budged

is considered, where n_CB is the number of code blocks within a TB (see Fig. 4c). By keeping track of the iterations that have been spent on previous code blocks belonging to the same TB, the Turbo-Code decoder is able to spent more decoding iterations on blocks that contain more errors, thereby using the iterations saved by the early stopping. To avoid the case where a single undecodable code block at the beginning of a TB consumes the complete iteration budget, the decoding for each code block is allowed to run for $\mathrm{4}\cdot n_{\mathrm{HI}}^{\max }$ half-iterations. Our investigations have shown that this value is a very good trade-off. As can be seen in Fig. 4c and as was shown in 2017a, iteration balancing can not only be used to improve the communications performance, but can also be used to guarantee a higher throughput on system level. For this work, however, we focus on the improvement in communications performance.

Figure 4Schedule for a TB with 6 code blocks: (a) No early stopping; (b) with early stopping; (c) Early stopping with HI Balancing.

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3.2 Enhanced high-rate decoding for short blocks

For LTE, code rates $r>\mathrm{1}/\mathrm{3}$ are achieved by puncturing the rate 1∕3 mother Turbo-Code (see Sect. 2.2). To limit the degradation of the Turbo-Code performance at code rates as high as 0.94, not only the parity information but also the systematic information is punctured. In recent work, we identified the positions where the systematic bit is punctured away as critical bit positions (see Weithoffer and Wehn, 2017b). We could show, that, if these positions are not correctly decoded by the decoder in the first few half-iterations, the decoding process is likely to fail, since the decoder has trouble recovering the correct hard decision bit for these positions in the later half-iterations. In LTE, the critical bit positons are at the bit indices

assuming the bit indices start at i=1. At high code rates, these critical positions exhibit the majority of residual errors after Turbo-Code decoding.

The remainder of this section describes new approaches to improve the decoding performance for small code blocks at high code rates on system level. In Sect. 4, we show, for the first time, the application of these system level techniques onto a fully LTE compatible hardware architecture on bit level.

3.2.1 Improved flip-and-check

Based on the error detection via CRC, we recently proposed in 2017b the improved flip-and-check (FC) method. The algorithm shown in Fig. 5 makes use of critical positions, that result from the puncturing, to increase the communications performance of the Turbo-Code decoding with a greatly reduced complexity compared to similar approaches like event flipping Crozier and Gracie (2008) or flip-and-check Tonnellier et al. (2016). It takes as input a set N of critical positions determined by Eq. (2), a set M of least reliable bit positions with $N\cup M=\mathrm{\varnothing }$ and a set of decoded hard decision bits. Then, the bits are flipped at the critical and least reliable positions for all combinations. The CRC is tested for the 2^N+M patterns and the CRC results are used as stopping criterion for the iteration control of a Turbo-Code decoder. However, in a state-of-the-art hardware implementation, the complete set of hard decisions and the set of least reliable bit positions is only known after each half iteration. Therefore, in this work, we further optimized the algorithm and integrated it into an on-the-fly CRC calculation scheme (see Sect. 4).

Figure 5Pseudocode for the improved iteration control.

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3.3 Communications performance simulations

The new LTE-A Turbo-Code decoder architecture, which will be presented in Sect. 4, incorporates for the first time enhanced event-flipping and forced symbol decoding on-the-fly to improve the communications performance for small code blocks at high code rates, as well as an iteration control with iteration balancing to improve communications performance on transport block level for high code rates. To put the communications performance into context, we performed detailed simulations to compare our new approach to other state-of-the-art Turbo-Code decoders achieving a similar throughput.

Table 1Algorithm parameters of LTE Turbo-Code decoders.

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Table 1 gives the algorithm parameters of the compared decoder architectures, while Table 2 lists the implementation related data. Our investigatons have shown N=4 and M=1 to be a good match for the LTE configuration, while still allowing an integration of the new on-the-fly flip-and-check CRC calculation scheme with negligible hardware overhead. The parameter o=4 results from the usable 16=2⁴ sub-decoder cores.

3.3.1 Impact of combined enhanced event-flipping and forced symbol decoding

Figure 6 shows the impact of the proposed enhanced event-flipping and forced symbol decoding for code block sizes $K=\mathrm{80},\mathrm{160},\mathrm{240}$ and rates 8∕9, and 0.94. For those small code bock sizes, commonly only one sub-decoder core is used for the decoding of the code block. Therefore, the communications performance for the decoders listed in Table 1 is approximated by that of a non-windowed serial max-Log-Map decoder (in the following called reference decoder) with an input quantization of 6 bit, an extrinsic scaling with 0.75, which decodes for $n_{\mathrm{HI}}^{\max }=\mathrm{12}$ half-iterations. Frame error rate (FER) simulations have been carried out over an additive white gaussian noise (AWGN) channel with BPSK modulation.

Figure 6FER over SNR for K<248 and: (a) rate $R=\mathrm{8}/\mathrm{9}$, (b) rate R=0.94.

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For rate 8∕9, coding gains of up to 1 dB at a target FER of 10⁻² can be observed over the reference decoder when decoding blocks with K=80. Coding gains of 0.9 and 0.3 dB over the reference decoder are achieved for K=160 and K=240 respectively.

Rate 0.94 allows the largest coding gains compared to the reference with 1.6 dB for K=80 and 0.6 dB for K=160 and K=240. Note, that, due to the steaper slopes of the FER curves, the coding gains for lower target FER values will be even larger.

3.3.2 Impact of iteration balancing

FER simulation results for a transport block size of 98 696 bit, which results in 16 code blocks of size 6144 illustrate the impact of iteration balancing for the proposed architecture in comparison to the state-of-the art architectures listed in Table 1. The decoding of 625 000 LTE-A transport blocks over an AWGN channel was simulated.

At rate 8∕9, the investigated decoders reach the target FER of 10⁻² at 3.9−4 dB (see Fig. 7a). For the single code block case (i.e. $B=n_{\mathrm{HI}}^{\max }=\mathrm{12}$), our decoder performs similar, reaching the target FER at 3.9 dB, while achieving a coding gain of 0.3–0.35 dB for the case of 16 code blocks.

For rate 0.94, the best performing reference decoders are the decoders from Shrestha and Paily (2014) and Roth et al. (2014) (see Fig. 7b). They reach the target FER of 10⁻² at an SNR of 5.1 dB while the decoder from Ilnseher et al. (2012) lies within 0.05 dB. Our decoder, if the single code block case is considered, achieves the target FER at around 5 dB. For the case of 16 code blocks, however, our decoder outperforms the reference decoders by 0.35–0.4 dB.

Figure 7FER over SNR for K=6144 and: (a) rate $R=\mathrm{8}/\mathrm{9}$, (b) rate R=0.94.

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4.1 Parallel symbol forcing

For the smallest LTE code block sizes, i.e. $\mathrm{40}\le K\le \mathrm{248}$, the decoder uses improved parallel symbol forcing to improve the communications performance. At design time, the available p=16 sub-decoder cores are assigned a sub-decoder index from 0–15.

While decoding, the extrinsic values at the critical positions are saturated after the first two half-iterations before being written to RAM. Saturation is performed according to a pattern that corresponds to their sub-decoder index. The extrinsic values for sub-decoder Map₀, for example, will be saturated to the maximum value for all four critcal positions. Figure 8 also illustrates the symbol forcing unit.

4.2 Flip-and-check extended crc unit

Figure 9 shows the structure of the FC extended CRC unit which is based on the on-the-fly architecture we presented in 2015. This section will describe the structure of the FC extended CRC unit and give the underlying equations where appropriate. For an in-depth derivation of the on-the-fly CRC calculation scheme, the reader is referred to the original publication (see Weithoffer and Wehn, 2015).

The CRC unit calculates the CRC over the decoded code word A(x) based on the following equation:

There, G(x) is the CRC generator polynomial of degree M, p is the parallelism , $S=K/p$ is the sub-block size, C_k is the sub-block offset and P_k is the partial sub-block CRC. In our case, it is G(x)=CRC_24B for which M=24 (see also Third Generation Partnership Project, 2016), p=16. A table lookup is used to realize the $C_k=\left(\mathrm{CRC}\right[x^{S-M}]{)}^k$ from Eq. (4) and this lookup table is initialized at the beginning of the decoding (C_k LUT in Fig. 9).

Figure 9FC enhanced on-the-fly CRC unit.

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Table 2Architecture parameters of LTE Turbo-Code decoders.

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The sub-block CRCs P_k for the sub-blocks are calculated according to

Dedicated blocks are used to calculate the partial CRCs CRC_even and CRC_odd for the hard decision bits a_kS+δ(2l) and $a_{kS+\mathit{\delta }(\mathrm{2}l+\mathrm{1})}$ respectively. The bit index offset for the kth sub-block is given by k⋅S and the function δ(l) describes the bit index offset within the sub-blocks according to

For efficient implementation, the sub-block internal bit index offset is broken down into $\mathit{\delta }=\mathrm{addr}/\mathrm{24}+\mathrm{addr}\mathrm{mod}\mathrm{24}$ (Divide by M in Fig. 9). Using these, CRC_even and CRC_odd are calculated with a combination of table lookup and dedicated block.

The FC extensions, which are used for the code blocks with $\mathrm{40}\le K\le \mathrm{248}$, consist of three parts:

• Selectively storing the partial CRCs for the critical positions,

• finding the most unreliable bit position and stroring the according partial CRC, and

• calculating the list of partial CRC combinations.

The partial CRCs for the critical positions are selected according to addr_even and stored in registers during the decoding phase. Note, that none of the partial CRCs for the critical positions are added to the P_k registers, which for $\mathrm{40}\le K\le \mathrm{248}$ serve as registers for the intermediate CRC result of each of the 16 sub-decoder cores.

The most unreliable bit position is selected and stored in parallel to the decoding, and individually for each sub-decoder core. If the current LLR-input to the CRC unit is of smaller magnitude than the previously stored one and the bit position is not included in the set of critical positions, the bit position (calculated from the address), its magnitude and its partial CRC are stored in registers. The same happens, when the magnitude is identical, but the bit index is smaller. Lastly, after decoding, the list of the ${\mathrm{2}}^{n+m}={\mathrm{2}}^{\mathrm{4}}=\mathrm{16}$ different combined sums of partial CRCs for the critical positions and the position with the minimum LLR is compiled and sent to the iteration control.

4.3 Iteration control

The iteration control uses iteration balancing with a configurable budget of B≤192 half-iterations (see Sect. 2.1). For transport blocks with more than one code block, the budget is reset at the start of the transport block. Transport blocks consisting of one code block use a budget of 12 half-iterations.

For all code block sizes, a CRC based early stopping is used. If the output from the CRC unit evaluates to 0 after the decoding of a half-iteration has finished, i.e. the CRC check is passed successfully, the decoding process is terminated early.

For code blocks with size $\mathrm{40}\le K\le \mathrm{248}$, however, a list of 32 CRC results is passed from each sub-decoder core. The decoding process is then terminated early if (at least) one decoder core has (at least) one succeeding CRC in the according list. If there are more than one successful CRCs whithin a list, the successful CRC with the smallest list index is chosen as the valid solution. Similarly, if there are more than one sub-decoder cores with a successful CRC in the same half-iteration, the result of the sub-decoder with the lower index is chosen as the correct result.

From the selected result, a correction pattern is generated and the address of the weakest LLR position is send to the output of the Turbo-Code decoder. Thereby, the hard decision bits can be corrected on-the-fly when they are read from the hard decision memory.