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Advances in Radio Science An open-access journal of the U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V.
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Volume 10
Adv. Radio Sci., 10, 175-181, 2012
https://doi.org/10.5194/ars-10-175-2012
© Author(s) 2012. This work is distributed under
the Creative Commons Attribution 3.0 License.
Adv. Radio Sci., 10, 175-181, 2012
https://doi.org/10.5194/ars-10-175-2012
© Author(s) 2012. This work is distributed under
the Creative Commons Attribution 3.0 License.

  18 Sep 2012

18 Sep 2012

Design space exploration of high throughput finite field multipliers for channel coding on Xilinx FPGAs

C. de Schryver, S. Weithoffer, U. Wasenmüller, and N. Wehn C. de Schryver et al.
  • Microelectronic Systems Design Research Group, University of Kaiserslautern, Erwin-Schrödinger-Str., Germany

Abstract. Channel coding is a standard technique in all wireless communication systems. In addition to the typically employed methods like convolutional coding, turbo coding or low density parity check (LDPC) coding, algebraic codes are used in many cases. For example, outer BCH coding is applied in the DVB-S2 standard for satellite TV broadcasting. A key operation for BCH and the related Reed-Solomon codes are multiplications in finite fields (Galois Fields), where extension fields of prime fields are used. A lot of architectures for multiplications in finite fields have been published over the last decades. This paper examines four different multiplier architectures in detail that offer the potential for very high throughputs. We investigate the implementation performance of these multipliers on FPGA technology in the context of channel coding. We study the efficiency of the multipliers with respect to area, frequency and throughput, as well as configurability and scalability. The implementation data of the fully verified circuits are provided for a Xilinx Virtex-4 device after place and route.

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