A new BIST scheme for low-power and high-resolution DAC testing

Li, H.; Eckmueller, J.; Sattler, S.; Eichfeld, H.; Weigel, R.

doi:https://doi.org/10.5194/ars-1-289-2003

Articles | Volume 1

https://doi.org/10.5194/ars-1-289-2003

© Author(s) 2003. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

https://doi.org/10.5194/ars-1-289-2003

© Author(s) 2003. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

Articles | Volume 1

05 May 2003

A new BIST scheme for low-power and high-resolution DAC testing

H. Li, J. Eckmueller, S. Sattler, H. Eichfeld, and R. Weigel

Abstract. A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals.