<?xml version="1.0" encoding="utf-8" standalone="no"?>
<!DOCTYPE article SYSTEM "http://www.adv-radio-sci.net/inc/ars/copernicus.dtd">
<article language="en">
	<journal>
		<journal_title>Advances in Radio Science</journal_title>
		<journal_url>www.adv-radio-sci.net</journal_url>
		<issn>1684-9965</issn>
		<eissn>1684-9973</eissn>
		<volume_number>7</volume_number>
		<volume_title>Kleinheubacher Berichte 2008</volume_title>
		<publication_year>2009</publication_year>
	</journal>
	<doi>10.5194/ars-7-225-2009</doi>
	<article_url>http://www.adv-radio-sci.net/7/225/2009/</article_url>
	<abstract_html>http://www.adv-radio-sci.net/7/225/2009/ars-7-225-2009.html</abstract_html>
	<fulltext_pdf>http://www.adv-radio-sci.net/7/225/2009/ars-7-225-2009.pdf</fulltext_pdf>
	<start_page>225</start_page>
	<end_page>229</end_page>
	<publication_date>2009-05-19</publication_date>
	<article_title content_type="html">Influence of gate tunneling currents on switched capacitor integrators</article_title>
	<authors>
		<author numeration="1" affiliations="1">
			<name>W. Kraus</name>
			<email>kraus@tum.de</email>
		</author>
		<author numeration="2" affiliations="1">
			<name>D. Schmitt-Landsiedel</name>
		</author>
	</authors>
	<affiliations>
		<affiliation numeration="1" content_type="html">Institute for Technical Electronics, Technische Universität München, Germany</affiliation>
	</affiliations>
	<abstract content_type="html">In order to achieve a higher level of integration
in modern VLSI systems, not only the lateral geometrical dimensions
have to be scaled. Lowering the supply voltage
also requires scaling down the oxide thickness of the transistors.
While the oxide thickness is scaled down proportionally
with the supply voltage, the gate tunneling currents grow exponentially,
which results in special issues concerning deviations
in charge based analog and mixed signal circuitry. The
influence of gate tunneling currents on this kind of circuits
will be demonstrated at a fully differential switched capacitor
integrator. The used process data is derived from the International
Technology Roadmap for Semiconductors (ITRS
Roadmap, 2006). The Parameter sets for the simulations are
based on the Predictive Technology Model of the Arizona
State University Modelling Group for the 65 nm Technology
node (Predictive Technology Model, 2008).</abstract>
	<references>
		<reference numeration="1" content_type="text"> ITRS Roadmap: Semiconductor Industry Association, The International Technology Roadmap for Semiconductors, http://www.itrs.net/, 2006. </reference>
		<reference numeration="2" content_type="text"> Predictive Technology Model: Nanoscale Integration and Modelling Group, Arizona State University, Predictive Technology Model, PTM, http://www.eas.asu.edu/~ptm/, 2008. </reference>
	</references>
</article>

