Advances in Radio Science www.adv-radio-sci.net 1684-9965 1684-9973 7 Kleinheubacher Berichte 2008 2009 10.5194/ars-7-107-2009 http://www.adv-radio-sci.net/7/107/2009/ http://www.adv-radio-sci.net/7/107/2009/ars-7-107-2009.html http://www.adv-radio-sci.net/7/107/2009/ars-7-107-2009.pdf 107 112 2009-05-18 Quantitative comparison of performance analysis techniques for modular and generic network-on-chip M. C. Neuenhahn J. Schleifer schleifer@eecs.rwth-aachen.de H. Blume T. G. Noll Chair for Electrical Engineering and Computer Systems, RWTH Aachen Univ., Schinkelstraße 2, 52062 Aachen, Germany NoC-specific parameters feature a huge impact on performance and implementation costs of NoC. Hence, performance and cost evaluation of these parameter-dependent NoC is crucial in different design-stages but the requirements on performance analysis differ from stage to stage. In an early design-stage an analysis technique featuring reduced complexity and limited accuracy can be applied, whereas in subsequent design-stages more accurate techniques are required. <br><br> In this work several performance analysis techniques at different levels of abstraction are presented and quantitatively compared. These techniques include a static performance analysis using timing-models, a Colored Petri Net-based approach, VHDL- and SystemC-based simulators and an FPGA-based emulator. Conducting NoC-experiments with NoC-sizes from 9 to 36 functional units and various traffic patterns, characteristics of these experiments concerning accuracy, complexity and effort are derived. <br><br> The performance analysis techniques discussed here are quantitatively evaluated and finally assigned to the appropriate design-stages in an automated NoC-design-flow. Altera Corporation: Nios II Processor Reference Handbook, Altera Corporation, 2007. Altera Corporation: Stratix II Device Handbook, Altera Corporation, 2007. Angiolini, F., Meloni, P., Carta, S., Benini, L., and Raffo, L.: Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness, in: Design, Automation and Test in Europe, DATE '06, 1–6, 2006. Bainbridge, J. and Furber, S.: Chain: a delay-insensitive chip area interconnect, IEEE Micro, 22, 16–23, 2002. Benini, L. and De Micheli, G.: Networks on chips: a new SoC paradigm, Computer, 35, 70–78, 2002. Bjerregaard, T. and Mahadevan, S.: A survey of research and practices of Network-on-chip, ACM Comput. Surv., 38, p 1, 2006. Blume, H., Feldkaemper, H. T., and Noll, T. G.: Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip, J. VLSI Signal Proc., 40, 19–34, 2005. Dick, R. P., Rhodes, D. L., and Wolf, W.: TGFF: task graphs for free, The Sixth International Workshop on Hardware/Software Codesign (CODES/CASHE '98), 97–101, 1998. Dotolia, M. and Fanti, M. P.: An Urban Traffic Network Model via Coloured Petri Nets, Control Eng. Pract., 14, 17~pp., 2006. Duato, J., Yalamanchili, S., and Ni, L.: Interconnection Networks – An Engineering Approach, San Francisco, USA, Morgan Kaufmann Publishers, 479-482, 2003. Girault, C. and Valk, R.: Petri Nets for Systems Engineering, Berlin, Springer, 9–68, 2004. IEEE: IEEE Std 1666–2005 IEEE Standard SystemC Language Reference Manual, IEEE Std 1666–2005, 0_1-423~pp., 2006. Jensen, K.: Net Models in System Development, Ph.D. thesis, Aarhus University, 1980. Mentor Graphics: ModelSim, Mentor Graphics, 2007. Neuenhahn, M. C., Blume, H., and Noll, T. G.: Quantitative analysis of network topologies for NoC-architectures on an FPGA-based emulator, Kleinheubacher Tagung, 2006. Neuenhahn, M. C., Blume, H., and Noll, T. G.: Quantitative Design Space Exploration of Routing-Switches for Network-on-Chip, Kleinheubacher Tagung Miltenberg, 145–150, 2007. Neuenhahn, M. C., Lemmer, D., Blume, H., and Noll, T. G.: Quantitative Cost Modeling of Error Protection for Network-on-Chip, ProRISC Workshop, Veldhoven, 331–337, 2007. Petri, C. A.: Kommunikation mit Automaten, Ph.D. thesis, Institut für instrumentelle Mathematik, Friedrich-Wilhelm-University Bonn, 1962. Schleifer, J., Blume, H., and Noll, T. G.: Performance Analysis of Networks on Chip Using Coloured Petri Nets, in: ProRISC 2008, Veldhoven, The Netherlands, 94–99, 2008. Shang, D. B., Koelmans, F., Yakovlev, A., and Xia, F.: Asynchronous system synthesis based on direct mapping using VHDL and Petri nets, IEE P.-Comput. Dig. T., 151, 12~pp., 2004. Tilera Corporation: TILE64\texttrademark Processor Product Brief, Tilera Corporation, 2007. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., and Borkar, N.: An 80-Tile 1.28TFLOPS Network-on-Chip in 65 nm CMOS, in: IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 98–589, 2007. Wielage, P. and Goossens, K.: Networks on silicon: blessing or nightmare?, in: Digital System Design, 196–200, 2002.