ARS - Volume 6, 2008 - D.5 Integrated digital circuits II

ARS - Volume 6, 2008

D.5 Integrated digital circuits II

ESD full chip simulation: HBM and CDM requirements and simulation approach E. Franell, S. Drueen, H. Gossner, and D. Schmitt-Landsiedel Page(s) 245-251 Abstract Full Article in PDF (PDF, 1005 KB)		26 May 2008
Untersuchung von asynchronen Timing-Strategien für digitale Subthreshold-Schaltungen N. Lotze, M. Ortmanns, and Y. Manoli Page(s) 253-258 Abstract Full Article in PDF (PDF, 133 KB)		26 May 2008
Hardware Accelerators for Elliptic Curve Cryptography C. Puttmann, J. Shokrollahi, M. Porrmann, and U. Rückert Page(s) 259-264 Abstract Full Article in PDF (PDF, 467 KB)		26 May 2008
Physical IC debug – backside approach and nanoscale challenge C. Boit, R. Schlangen, A. Glowacki, U. Kindereit, T. Kiyan, U. Kerst, T. Lundquist, S. Kasapi, and H. Suzuki Page(s) 265-272 Abstract Full Article in PDF (PDF, 1268 KB)		26 May 2008