Advances in Radio Science www.adv-radio-sci.net 1684-9965 1684-9973 6 Kleinheubacher Berichte 2007 2008 10.5194/ars-6-265-2008 http://www.adv-radio-sci.net/6/265/2008/ http://www.adv-radio-sci.net/6/265/2008/ars-6-265-2008.html http://www.adv-radio-sci.net/6/265/2008/ars-6-265-2008.pdf 265 272 2008-05-26 Physical IC debug – backside approach and nanoscale challenge C. Boit R. Schlangen A. Glowacki U. Kindereit T. Kiyan U. Kerst T. Lundquist S. Kasapi H. Suzuki TUB Berlin University of Technology, Berlin, Germany DCG Systems, Fremont, CA, USA NVIDIA, Santa Clara, CA, USA Hamamatsu Photonics KK, Japan Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach. Barton, D., Cole, Jr. E., and Bernhard-Höfer, K.: Flip Chip and "Backside" Sample Preparation Techniques, Microelectronics Failure Analysis Desk Reference, ASM International, 5th Edition, 42–48, Ohio, USA, 2004. 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