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www.adv-radio-sci.net/6/113/2008/
doi:10.5194/ars-6-113-2008
© Author(s) 2008. This work is distributed
under the Creative Commons Attribution 3.0 License.
Comparison of reconfigurable structures for flexible word-length multiplication
1Microelectronics Department, University of Ulm, Germany
2Electrical and Computer Engineering Department, The Hong Kong University of Science and Technology, Hong Kong S.A.R.
Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications.
In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.
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Citation: Pfänder, O. A., Nopper, R., Pfleiderer, H.-J., Zhou, S., and Bermak, A.: Comparison of reconfigurable structures for flexible word-length multiplication, Adv. Radio Sci., 6, 113-118, doi:10.5194/ars-6-113-2008, 2008. Bibtex EndNote Reference Manager XML
