Advances in Radio Science
www.adv-radio-sci.net
1684-9965
1684-9973
5
Kleinheubacher Berichte 2006
2007
10.5194/ars-5-285-2007
http://www.adv-radio-sci.net/5/285/2007/
http://www.adv-radio-sci.net/5/285/2007/ars-5-285-2007.html
http://www.adv-radio-sci.net/5/285/2007/ars-5-285-2007.pdf
285
290
2007-06-13
Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects
M. Fulde
fulde@tum.de
J. P. Engelstädter
G. Knoblinger
D. Schmitt-Landsiedel
Institute of Technical Electronics, Technical University Munich, Germany
Infineon Technologies AG, Villach, Austria
Department of Electrical Engineering, RWTH Aachen University, Aachen, Germany
Multi-gate FET, e.g. FinFET devices are the most promising contenders to
replace bulk FETs in sub-45 nm CMOS technologies due to their improved sub
threshold and short channel behavior, associated with low leakage currents.
The introduction of novel gate stack materials (e.g. metal gate, high-k
dielectric) and modified device architectures (e.g. fully depleted, undoped
fins) affect the analog device properties significantly. First measurements
indicate enhanced intrinsic gain (<i>g<sub>m</sub>/g<sub>DS</sub></i>) and promising matching
behavior of FinFETs. The resulting benefits regarding the
speed-accuracy-power trade-off in analog circuit design will be shown in this
work. Additionally novel device specific effects will be discussed. The
hysteresis effect caused by charge trapping in high-k dielectrics or
self-heating due to the high thermal resistor of the BOX isolation are
possible challenges for analog design in these emerging technologies. To gain
an early assessment of the impact of such parasitic effects SPICE based
models are derived and applied in analog building blocks.
Bertolissi, L.: Modeling and Simulation of Self-Heating Effects in Deep Sub-Micron Silicon on Insulator (SOI) Technologies for Analog Circuits, Ph.D. thesis, Universita Degli Studi di Udine, 2004.
Colinge, J.-P.: Novel Gate Concepts for MOS devices, in: IEEE Proceedings of the 34th European Solid-State Device Research conference, ESSDERC, 45–49, 2004.
Decoutere, S.: Perspectives of Downscaled CMOS for RFIC and mm-wave Applications, in: IEEE MTT-S International Microwave Symposium, 2006.
Fulde, M., Schmitt-Landsiedel, D., and Knoblinger, G.: Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits, in: Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS, 2007.
Gustin, C., Mercha, A., Loo, J., Subramanian, V., Parvais, B., Dehan, M., and Decoutere, S.: Stochastic Matching Properties of FinFETs, IEEE Electron Device Letters, 27, 846–848, 2006.
Kinget, P. and Steyaert, M.: Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits, in: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 1996, 333–336, 1996.
Knoblinger, G., Kuttner, F., Marshall, A., Russ, C., Haibach, P., Patruno, P., Schulz, T., Xiong, W., Gostkowski, M., Schruefer, K., and Cleavelin, C.: Design and evaluation of basic analog circuits in an emerging MuGFET technology, in: Proceedings of the IEEE International SOI Conference, 39–40, 2005.
Molzer~et al., W.: Self Heating Simulation of Multi-Gate FETs, in: IEEE Proceedings of 36th European Solid-State Device Research conference, ESSDERC, 311–314, 2006.
Pacha, C., von Arnim, K., Schulz, T., Xiong, W., Gostkowski, M., Knoblinger, G., Marshall, A., Nirschl, T., Berthold, J., Russ, C., Gossner, H., Duvvury, C., Patruno, P., Cleavelin, R., and Schruefer, K.: Circuit design issues in multi-gate FET CMOS technologies, in: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1656–1665, 2006.
Parvais, B., Gustin, C., de~Heyn, V., Loo, J., Dehan, M., Subramanian, V., Mercha, A., Collaert, N., Rooyackers, R., Jurczak, M., Wambacq, P., and Decoutere, S.: Suitability of FinFET technology for low-power mixed-signal applications, in: IEEE International Conference on Integrated Circuit Design and Technology, ICICDT '06, 1–4, 2006.
Pelgrom, M., Duinmaijer, A., and Welbers, A.: Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, 24, 1433–1439, 1989.
Ribes, G., Mitard, J., Denais, M., Bruyere, S., Monsieur, F., Parthasarathy, C., Vincent, E., and Ghibaudo, G.: Review on high-k dielectrics reliability issues, Device and Materials Reliability, IEEE Transactions on, 5, 5–19, 2005.
Schulz, T., Xiong, W., Cleavelin, C., Schruefer, K., Gostkowski, M., Matthews, K., Gebara, G., Zaman, R., Patruno, P., Chaudhry, A., Woo, A., and Colinge, J.: Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs), in: Proceedings of the IEEE International SOI Conference, 154–156, 2005.
Tewksbury, T.L., I. and Lee, H.-S.: Characterization, modeling, and minimization of transient thresholdvoltage shifts in MOSFETs, IEEE Journal of Solid-State Circuits, 29, 239–252, 1994.
van~den Bosch, A., Borremans, M., Steyaert, M., and Sansen, W.: A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter, IEEE Journal of Solid-State Circuits, 36, 315–324, 2001.