| Volumes Volume 4 |
ARS - Volume 4, 2006
D.1 Integrierte digitale und analoge Schaltungen| IQ-imbalance and its compensation for non-ideal analog receivers comprising frequency-selective components Page(s) 189-195 Abstract Full Article in PDF (PDF, 1337 KB) | ||
| Timing violations due to VDD/VSS bounce Page(s) 197-205 Abstract Full Article in PDF (PDF, 3324 KB) | ||
| Full dynamic resolution low lower DA-Converters for flat panel displays Page(s) 207-212 Abstract Full Article in PDF (PDF, 288 KB) | ||
| Ultra Low Power Bandgap Strom- und Spannungsquellen in CMOS-Technologie für integrierte drahtlose Systeme Page(s) 213-217 Abstract Full Article in PDF (PDF, 210 KB) | ||
| LNA for Low-Power, Low Data Rate PAN Applications Page(s) 219-224 Abstract Full Article in PDF (PDF, 309 KB) | ||
| Yield-improving test and routing circuits for a novel 3-D interconnect technology Page(s) 225-229 Abstract Full Article in PDF (PDF, 283 KB) | ||
| Configurable multiplier modules for an adaptive computing system Page(s) 231-236 Abstract Full Article in PDF (PDF, 146 KB) | ||
| Auswirkungen der Quantisierung bei nichtlinearen Funktionen Page(s) 237-242 Abstract Full Article in PDF (PDF, 126 KB) | ||
| A 10 bit very low-power CMOS SAR-ADC for capacitive micro-mechanical pressure measurement in implants Page(s) 243-246 Abstract Full Article in PDF (PDF, 467 KB) | ||
| An integrated 3.1–5.1 GHz pulse generator for ultra-wideband wireless localization systems Page(s) 247-250 Abstract Full Article in PDF (PDF, 976 KB) | ||
| Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic Page(s) 251-257 Abstract Full Article in PDF (PDF, 2466 KB) | ||
| Towards a generic operational amplifier with dynamic reconfiguration capability Page(s) 259-262 Abstract Full Article in PDF (PDF, 1278 KB) | ||
| Rekonfigurationstechniken und Anwendungsgebiete für ein programmierbares Gm-C Analog-Filter Page(s) 263-267 Abstract Full Article in PDF (PDF, 661 KB) | ||
| Monotonic transition based forward body bias for dual threshold voltage low power embedded processors Page(s) 269-273 Abstract Full Article in PDF (PDF, 2379 KB) | ||
| Power-Clock-Gating in adiabatischen Logikschaltungen Page(s) 275-280 Abstract Full Article in PDF (PDF, 97 KB) | ||
| Modelling of the parametric yield in decananometer SRAM-Arrays Page(s) 281-285 Abstract Full Article in PDF (PDF, 309 KB) | ||
| 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator Page(s) 287-291 Abstract Full Article in PDF (PDF, 1985 KB) | ||
| On the synthesis and optimization of cascaded continuous-time Sigma-Delta modulators Page(s) 293-297 Abstract Full Article in PDF (PDF, 451 KB) | ||
| Neuartige, differentiell gespeiste Transmissionsleitung auf Silicium Page(s) 299-302 Abstract Full Article in PDF (PDF, 132 KB) | ||
| A Verilog-A model of an undoped symmetric dual-gate MOSFET Page(s) 303-306 Abstract Full Article in PDF (PDF, 162 KB) | ||
| Simulation von CNFET basierten Digitalschaltungen Page(s) 307-311 Abstract Full Article in PDF (PDF, 1056 KB) | ||
| From algorithm to implementation: a case study on blind carrier synchronization Page(s) 313-318 Abstract Full Article in PDF (PDF, 232 KB) | ||
| Automatisierte VHDL-Code-Generierung eines Delta-Sigma Modulators Page(s) 319-322 Abstract Full Article in PDF (PDF, 1343 KB) |
