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Advances in Radio Science An open-access journal of the U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V.

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Adv. Radio Sci., 4, 287-291, 2006
http://www.adv-radio-sci.net/4/287/2006/
doi:10.5194/ars-4-287-2006
© Author(s) 2006. This work is licensed under the
Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.
 
06 Sep 2006
2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator
S. Tontisirin and R. Tielert Technische Universität Kaiserslautern, Germany
Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.

Citation: Tontisirin, S. and Tielert, R.: 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator, Adv. Radio Sci., 4, 287-291, doi:10.5194/ars-4-287-2006, 2006.
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