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Yield-improving test and routing circuits for a novel 3-D interconnect technology
1University of Ulm, Microelectronics Department, Albert-Einstein-Allee 43, 89081 Ulm, Germany
2University of Ulm, Department of Electron Devices and Circuits, Germany
3Infineon Technologies AG, Germany
Abstract. This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high.
The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production.
Full Article in PDF (PDF, 283 KB)
Citation: Bschorr, M., Pfleiderer, H.-J., Benkart, P., Kaiser, A., Munding, A., Kohn, E., Heittmann, A., Hübner, H., and Ramacher, U.: Yield-improving test and routing circuits for a novel 3-D interconnect technology, Adv. Radio Sci., 4, 225-229, 2006. Bibtex EndNote Reference Manager
