Advances in Radio Science
www.adv-radio-sci.net
1684-9965
1684-9973
4
Kleinheubacher Berichte 2005
2006
10.5194/ars-4-197-2006
http://www.adv-radio-sci.net/4/197/2006/
http://www.adv-radio-sci.net/4/197/2006/ars-4-197-2006.html
http://www.adv-radio-sci.net/4/197/2006/ars-4-197-2006.pdf
197
205
2006-09-06
Timing violations due to <i>V<sub>DD</sub>/V<sub>SS</sub></i> bounce
M. Eireiner
eireiner@tum.de
S. Henzler
J. Berthold
C. Pacha
G. Georgakos
D. Schmitt-Landsiedel
Institute for Technical Electronics, Technical University Munich, Germany
Infineon Technologies, Munich, Germany
The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.
Benoit, M., Taylor, S., Overhauser, D., and Rochel, S.: Power Distribution in High-Performance Design, in: International Symposium on Low Power Electronics and Design, 1998.
Ernst, D., Austin, D. B T., Flautner, K., Mudge, T., and et~al: Razor: A low-power pipeline based on circuit-level timing speculation, in: Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO-36), IEEE CS Press, 7–18, 2003.
Henzler, S., Nirschl, T., Berthold, J., Georgakos, G., and Schmitt-Landsiedel, D.: Design and Technology of Fine-Grained Sleep Transistor Circuits in Ultra-Deep Sub-Micron CMOS Technologies, in: Proceedings of International Conference on Integrated Circuit Design and Technology, 2005.
http://www.itrs.net: International Roadmap for Semiconductors, Tech. rep., ITRS, 2003.
Lin, S. and Chang, N.: Challenges in Power-Ground Integrity., in: ICCAD, 651, 2001.
Piguet, C., ed.: Low-Power Electronics Design, CRC Press, 2004.
Rusu, S., Tam, S., Muljono, H., Ayers, D., and Chang, J.: A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache, in: Digest of Technical Papers. ISSCC, 102–103, 2006.
Tschanz, J., Kao, J., Narendra, S., Nair, R., Antoniadis, D., Chandrakasan, A., and De, V.: Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, in: Digest of Technical Papers. ISSCC, 2, 2002.