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Timing violations due to VDD/VSS bounce
1Institute for Technical Electronics, Technical University Munich, Germany
2Infineon Technologies, Munich, Germany
Abstract. The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.
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Citation: Eireiner, M., Henzler, S., Berthold, J., Pacha, C., Georgakos, G., and Schmitt-Landsiedel, D.: Timing violations due to VDD/VSS bounce, Adv. Radio Sci., 4, 197-205, 2006. Bibtex EndNote Reference Manager
