| Volumes Volume 3 |
ARS - Volume 3, 2005
D.1 Integrierte digitale und analoge SchaltungenEditor(s): H. Klar
| Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs Page(s) 271-276 Abstract Full Article in PDF (PDF, 656 KB) | ||
| A 8X Oversampling Ratio, 14bit, 5-MSamples/s Cascade 3-1 Sigma-delta Modulator Page(s) 277-280 Abstract Full Article in PDF (PDF, 178 KB) | ||
| Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits Page(s) 281-285 Abstract Full Article in PDF (PDF, 450 KB) | ||
| Digitalsimulator für pulscodierte neuronale Netze Page(s) 287-291 Abstract Full Article in PDF (PDF, 248 KB) | ||
| 10Gb/s Bang-Bang Clock and Data Recovery (CDR) for optical transmission systems Page(s) 293-297 Abstract Full Article in PDF (PDF, 1052 KB) | ||
| Design of a LNA in the frequency band 1.8-2.2GHz in 0.13μm CMOS Technology Page(s) 299-303 Abstract Full Article in PDF (PDF, 944 KB) | ||
| Eine Test- und Ansteuerschaltung für eine neuartige 3D Verbindungstechnologie Page(s) 305-310 Abstract Full Article in PDF (PDF, 740 KB) | ||
| Impact of Level-Converter on Power-Saving Capability of Clustered Voltage Scaling Page(s) 311-317 Abstract Full Article in PDF (PDF, 555 KB) | ||
| Dynamische Rekonfiguration von arithmetischen Einheiten auf Bitebene Page(s) 319-323 Abstract Full Article in PDF (PDF, 344 KB) | ||
| An Adiabatic Architecture for Linear Signal Processing Page(s) 325-329 Abstract Full Article in PDF (PDF, 1049 KB) | ||
| Noise Considerations of Integrators for Current Readout Circuits Page(s) 331-336 Abstract Full Article in PDF (PDF, 122 KB) | ||
| Design Space Exploration for Frequency Synchronization of BPSK/QPSK Bursts Page(s) 337-341 Abstract Full Article in PDF (PDF, 311 KB) | ||
| Analytische Betrachtung des Quantisierungsfehlers bei grundlegenden Rechenoperationen der digitalen Signalverarbeitung Page(s) 343-347 Abstract Full Article in PDF (PDF, 419 KB) | ||
| Determination of Harmonic-Transfer-Matrices by Simulation Page(s) 349-354 Abstract Full Article in PDF (PDF, 235 KB) | ||
| A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies Page(s) 355-358 Abstract Full Article in PDF (PDF, 221 KB) | ||
| Design and Analysis of Fully Integrated Differential VCOs Page(s) 359-363 Abstract Full Article in PDF (PDF, 1754 KB) | ||
| Analysis and Simulation of Reduced FIR Filters Page(s) 365-369 Abstract Full Article in PDF (PDF, 167 KB) | ||
| Eine FPAA-Architektur zur rekonfigurierbaren Instantiierung von zeitkontinuierlichen Analogfiltern Page(s) 371-375 Abstract Full Article in PDF (PDF, 187 KB) | ||
| Challenges of VDD scaling for analog circuits: an amplifier Page(s) 377-381 Abstract Full Article in PDF (PDF, 467 KB) | ||
| A Contribution to Reconfigurable Analog Electronics by a Digitally Programmable Sensor Signal Amplifier Page(s) 383-388 Abstract Full Article in PDF (PDF, 1115 KB) | ||
| Implementierung eines verlustleistungsoptimierten Dezimators für kaskadierte Sigma-Delta Analog-Digital Umsetzer Page(s) 389-393 Abstract Full Article in PDF (PDF, 303 KB) |
