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An Adiabatic Architecture for Linear Signal Processing
University of Dortmund, Information Processing Lab., Germany
Abstract. Using adiabatic CMOS logic instead of the more traditional static CMOS logic can lower the power consumption of a hardware design. However, the characteristic differences between adiabatic and static logic, such as a four-phase clock, have a far reaching influence on the design itself. These influences are investigated in this paper by adapting a systolic array of CORDIC devices to be implemented adiabatically.
We present a means to describe adiabatic logic in VHDL and use it to define the systolic array with precise timing and bit-true calculations. The large pipeline bubbles that occur in a naive version of this array are identified and removed to a large degree. As an example, we demonstrate a parameterization of the CORDIC array that carries out adaptive RLS filtering.
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Citation: Vollmer, M. and Götze, J.: An Adiabatic Architecture for Linear Signal Processing, Adv. Radio Sci., 3, 325-329, 2005. Bibtex EndNote Reference Manager
