| Volumes Volume 2 |
ARS - Volume 2, 2004
D.1 Integrierte digitale und analoge SchaltungenEditor(s): Klar, H.
| Testen komplexer digitaler Schaltungen mit Python Page(s) 175-179 Abstract Full Article in PDF (PDF, 81 KB) | ||
| Application driven evaluation of network on chip architectures forcation parallel signal processing Page(s) 181-186 Abstract Full Article in PDF (PDF, 228 KB) | ||
| Different approaches of high speed data transmission standards Page(s) 187-193 Abstract Full Article in PDF (PDF, 2449 KB) | ||
| GPS low noise amplifier with high immunity to wireless jamming signals and power control option Page(s) 195-197 Abstract Full Article in PDF (PDF, 473 KB) | ||
| Eine verlustleistungsoptimierte Dezimator-Architektur für kaskadierte Sigma-Delta Analog-Digital Umsetzer Page(s) 199-203 Abstract Full Article in PDF (PDF, 413 KB) | ||
| Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2 Page(s) 205-209 Abstract Full Article in PDF (PDF, 686 KB) | ||
| Consideration of parasitic effects on buses during early IC design stages Page(s) 211-214 Abstract Full Article in PDF (PDF, 329 KB) | ||
| Power estimation on functional level for programmable processors Page(s) 215-219 Abstract Full Article in PDF (PDF, 1298 KB) | ||
| Improving the positive feedback adiabatic logic familiy Page(s) 221-225 Abstract Full Article in PDF (PDF, 214 KB) | ||
| Theory of circuit block switch-off Page(s) 227-232 Abstract Full Article in PDF (PDF, 685 KB) | ||
| Circuit architecture derivation starting from a formal requirements specification considering a DDS as example Page(s) 233-236 Abstract Full Article in PDF (PDF, 510 KB) |
