Positive Feedback Adiabatic Logic (PFAL) shows the lowest energy dissipation among adiabatic logic families based on cross-coupled transistors, due to the reduction of both adiabatic and non-adiabatic losses. The dissipation primarily depends on the resistance of the charging path, which consists of a single p-channel MOSFET during the recovery phase. In this paper, a new logic family called Improved PFAL (IPFAL) is proposed, where all n- and pchannel devices are swapped so that the charge can be recovered through an n-channel MOSFET. This allows to decrease the resistance of the charging path up to a factor of 2, and it enables a significant reduction of the energy dissipation. Simulations based on a 0.13µm CMOS process confirm the improvements in terms of power consumption over a large frequency range. However, the same simple design rule, which enables in PFAL an additional reduction of the dissipation by optimal transistor sizing, does not apply to IPFAL. Therefore, the influence of several sources of dissipation for a generic IPFAL gate is illustrated and discussed, in order to lower the power consumption and achieve better performance.