An 8 bit current steering DAC for offset compensation purposes in sensor arrays
1Chair of Sensor and Actuator Systems, TU Berlin, Berlin, Germany
2ARCES, University of Bologna, Bologna, Italy
Abstract. An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10 μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 μW at 2.6 MHz operation frequency. Total area is 38.6 × 2933.0 μm2.
Bertotti, G., Laifi, A., Di Gioia, E., Masoumi, M., Dodel, N., Scarselli, E. F., and Thewes, R.: An 8 bit current steering DAC for offset compensation purposes in sensor arrays, Adv. Radio Sci., 10, 201-206, doi:10.5194/ars-10-201-2012, 2012.