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www.adv-radio-sci.net/1/289/2003/
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A new BIST scheme for low-power and high-resolution DAC testing
1SMS TI MT MS, Infineon AG, Postfach 80 09 49, D-81609 München, Germany
2CTT TS ADT, Infineon AG, Postfach 80 09 49, D-81609 München, Germany
3Lehrstuhl Technische Elektronik, Friedrich-Alexander-Universität Erlangen-Nürnberg, Cauerstr. 9, 91058 Erlangen, Germany
Abstract. A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals.
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Citation: Li, H., Eckmueller, J., Sattler, S., Eichfeld, H., and Weigel, R.: A new BIST scheme for low-power and high-resolution DAC testing, Adv. Radio Sci., 1, 289-293, 2003. Bibtex EndNote Reference Manager
